| Electronic Components Datasheet Search |
|
AVR32AP Datasheet(PDF) 50 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AVR32AP Datasheet(HTML) 50 Page - ATMEL Corporation |
|
50 / 181 page ![]() 50 32001A–AVR32–06/06 AVR32 Figure 4-2. The AVR32 segment translation map 4.2 Understanding the MMU The AVR32 Memory Management Unit (MMU) is responsible for mapping virtual to physical addresses. When a memory access is performed, the MMU translates the virtual address speci- fied into a physical address, while checking the access permissions. If an error occurs in the translation process, or operating system intervention is needed for some reason, the MMU will issue an exception, allowing the problem to be resolved by software. The MMU architecture uses paging to map memory pages from the 32-bit virtual address space to a 32-bit physical address space. Page sizes of 1, 4, 64 Kbytes and 1 Mbyte are supported. Each page has individual access rights, providing fine protection granularity. The information needed in order to perform the virtual-to-physical mapping resides in a page table. Each page has its own entry in the page table. The page table also contains protection information and other data needed in the translation process. Conceptually, the page table is accessed for every memory access, in order to read the mapping information for each page. 4.2.1 Virtual Memory Models The MMU provides two different virtual memory models, selected by the Mode (M) bit in the MMU Control Register: • Shared virtual memory, where the same virtual address space is shared between all processes • Private virtual memory, where each process has its own virtual address space In shared virtual memory, the virtual address uniquely identifies which physical address it should be mapped to. Two different processes addressing the same virtual address will always access 2GB translated space cacheable 512MB system space, non-cacheable 512MB translated space, cacheable 512MB non-translated space, non-cacheable 512MB non-translated space, cacheable 0x00000000 0x80000000 0xA0000000 0xC0000000 0xE0000000 0xFFFFFFFF P0 / U0 P1 P2 P3 P4 2GB physical address space Virtual address space 512MB physical address space 0x00000000 0x80000000 0xE0000000 0xFFFFFFFF 0x20000000 Physical address space Segment translation |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |