AVR32AP datasheet(30/181 Pages) ATMEL

30 / 181 page

32001A–AVR32–06/06

AVR32

labeled flushedaddress that must be flushed from the cache. INVALIDATEI is a macro that is

defined to be the command for invalidation of the icache.

cache

INVALIDATEI

nop

rjmp flushedaddress

3.9.6

Hazards on the Q flag

Some of the instructions in the instruction set updates the status register Q flag. Many of these

instructions, like satadd, generate the new Q flag after a single cycle so no hazards are present

between these instructions and other instructions. The sats, satu, satrnds, satrndu and some

multiply instructions, require several cycles before updating the Q flag. The required Q flag

latency for each of these instructions is listed in Section 10. on page 154. The user must make

sure that any of these instructions have completed and updated the Q flag before using the Q

flag in any computations. In the following example, a satrnds instruction is followed by a branch-

if-q-set instruction. A nop is needed in order to guarantee correct execution.

satrnds

r0>>0, 5

nop

brqs targetaddress

3.10

Event handling

The CPU is able to respond to different events. An event can be either an interrupt or an excep-

tion. Interrupts are requests from external modules and are routed through the interrupt

controller. Exceptions are system events that require handling outside normal program flow.

Different types of exceptions can occur during execution of an instruction. Some exceptions are

instruction-address related, and occur during instruction fetch. Other exceptions occur during

decode, like unimplemented instruction and illegal opcode. Data access instructions can cause

data-address related exceptions, like DTLB miss. Exceptions can occur in different pipe stages,

depending on the type of exception. Several exceptions can be related to the same instruction.

Mechanisms must therefore be implemented so that several exceptions associated with the

same instruction can be handled correctly. The exception priorities are defined Table 3-2 on

page 34. An instruction that has caused an exception request is called a contaminated

instruction.

Each pipeline stage has a pipeline register that holds the exception requests associated with the

instruction in that pipeline stage. This allows the exception request to follow the contaminated

instruction through the pipeline.

Events are detected in two different pipeline stages. The D stage detects all data-address

related exceptions (DTLB multiple hit, DTLB miss, DTLB protection and DTLB modified). All

other exceptions and interrupts are detected in the A1 stage. Data breakpoints are also detected

in A1.

A complication occurs with the event detection in the A1 stage: The instruction tagged as con-

taminated may be part of a folded branch. In this case, the event is taken only if the branch

prediction was correct. Otherwise, the entire folded branch instruction is flushed.

Data-address related exceptions are detected in the D stage. The address boundary check unit

ensures that no sequential instructions are issued unless it can be guaranteed that the data

access will not generate an exception.

AVR32AP Datasheet(PDF) 30 Page - ATMEL Corporation

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