AVR32AP datasheet(96/181 Pages) ATMEL

96 / 181 page

32001A–AVR32–06/06

AVR32

9.2.4.10

Abort command

Some software errors could cause the CPU to get stuck in a state which does not allow Debug

Mode to be entered through the mechanisms described above. An example is if a privileged

mode writes SR:DM to one, without clearing the bit.

To prevent the debugger from hanging indefinitely, the debugger can write the DC:ABORT bit to

one after some timeout period, and force the CPU to enter Debug Mode. The abort command

behaves identical to a debug request, except that the DM bit and any pending exception will be

ignored, regardless of exception priority. The RAR_DBG and RSR_DBG will reflect the last non-

executed instruction, which can aid in locating the error.

If Debug Mode is entered due to an abort command, DS:DBA will be set, as for debug requests.

9.2.5

Exceptions and Debug Mode

Debug Mode has priority over any execution mode, so that breakpoints can be set in exception

and interrupt routines. However, if a breakpoint is set on an instruction which triggers a critical

exception, the breakpoint is flushed. Critical exceptions are exception which are asynchronous

to the CPU (interrupts), exceptions which invalidate the currently fetched instruction (e.g.

instruction address exceptions), and exceptions which indicate that the system has become

unstable and should abort the program flow (e.g. bus error). The complete list of exceptions with

higher priority than Debug Mode are listed in the exception chapter in the AVR32 Architecture

Manual.

If a PC breakpoint, a breakpoint instruction, or a trapped 0x0000 opcode is flushed by an excep-

tion, Debug Mode will not be entered. If another type of breakpoint has triggered, Debug Mode

will be entered on the first instruction in the exception handler.

In the rare cases where the first instruction in a critical exception also triggers a critical exception

(e.g. if EVBA is set incorrectly, triggering an infinite loop of instruction address exceptions), the

debugger must write the DC:ABORT bit to one to halt the CPU and enter Debug Mode to identify

the error.

9.2.6

Instruction replacement

A convenient way of implementing an unlimited number of instruction breakpoints is letting the

debugger replace an instruction by a breakpoint instruction. This mechanism is only available in

OCD Mode on devices implemented with writeable program memory or writeable instruction

cache. If this instruction executes, Debug Mode will be entered, and the debugger identifies the

breakpointed location. When returning, the breakpoint instruction must be replaced by the origi-

nal instruction. The debugger will write the Instruction Replace (IRP) bit in DC and the

appropriate instruction in the Debug Instruction Register and its corresponding PC value in the

Debug Program Counter (DPC). When retd is executed, PC and SR are restored, but one more

instruction is fetched from the OCD system before returning to fetching from program memory.

Note that instruction replacement operates on word boundaries. The debugger must store the

whole word containing the replaced opcode before inserting the breakpoint instruction. Also note

that DPC should always be written when performing an instruction replacement to ensure the

correct instruction is executed.

The debugger will then perform the following sequence when exiting OCD Mode. Note that

RAR_DBG is accessed through executing CPU instructions through the Debug Instruction regis-

ter (DINST). The same sequence can be used both for compact and extended instructions,

regardless if the extended instruction is unaligned (in which case only the upper halfword of the

instruction is replaced).

AVR32AP Datasheet(PDF) 96 Page - ATMEL Corporation

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