AVR32AP datasheet(98/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

9.2.7

Sleep Mode

If the CPU is in sleep mode, it will not receive clocks nor respond to an OCD request from the

debugger. Thus, if the Debug Request bit in DC is written to one while the CPU is in sleep mode,

the CPU will automatically return to active mode. The instruction following the sleep instruction

will be tagged with an OCD exception, and the CPU will jump directly to Debug Mode. The nor-

mal debug procedure can be followed while executing in Debug Mode. If Debug Mode is entered

from sleep mode, the Stop Status (STP) bit in the Development Status register will be set.

When returning from Debug Mode, the CPU will by default return to the instruction following the

sleep instruction. The debugger can handle this situation in two ways:

Allow the CPU to wake up from sleep mode on a debug request.

Decrement RAR_DBG in Debug Mode to return to the sleep instruction. This places the

CPU back into sleep mode after exiting Debug Mode.

9.2.8

OCD Register Access

The OCD registers control the OCD system. Their specification is based on the Nexus Recom-

mended Registers as outlined in the Nexus Standard Specification [IEEE-ISTO 5001™-2003].

All registers can be accessed through the JTAG interface.

9.2.9

OCD features in Debug Mode

When the CPU executes in Debug Mode, certain OCD features will be disabled. The following

table indicates how the various OCD features will behave in Debug Mode. For more information

on the specific features, please see the indicated page.

9.2.10

OCD Registers Accessed by CPU

A monitor program running on the target can access the OCD registers through mtdr and mfdr

instructions. These instructions transfer data between a register in the register file and an OCD

instructions can also be used in OCD mode to transfer information from the register file and sys-

tem registers to the debugger, through the Debug Communication Mechanism.

Table 9-2.

OCD features in Debug Mode

Feature

Available in Debug Mode?

Program Breakpoints (HW)

Yes, in Monitor Mode when SR:DM is cleared

Software Breakpoints

Yes, in Monitor Mode when SR:DM is cleared

Data Breakpoints

Yes, in Monitor Mode when SR:DM is cleared

Watchpoints (program and data)

Yes, in Monitor Mode

Program Trace

Data Trace

Ownership Trace

Yes

NanoTrace

Direct Memory Access

Yes

Debug Communication Mechanism

Yes

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