AVR32AP datasheet(92/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

9.2.2.1

Debugging a monitor code

Each execution mode has a mask bit in SR, which indicates if a request to enter that mode will

be taken or masked. The default priority of modes are reflected in these bits: When entering an

execution mode, modes of the same or lower priority are masked. Privileged modes can over-

ride the mask, to dynamically change priorities (e.g. to allow critical interrupts to be serviced).

By default, Debug Mode has priority above all other execution modes. This implies that any

supervisor or user code can be interrupted by Debug Mode. Other modes can be explicitly

unmasked by a monitor code to allow critical interrupts to be serviced. By default, Debug Mode

is masked by the Debug Mask (DM) bit in SR when executing in Monitor Mode. The Monitor

Mode can stack away the RAR_DBG and RSR_DBG and then explicitly clear the DM bit to

enable Debug Mode to be re-entered. If a debug exception occurs in Monitor Mode, the OCD

system will bring the CPU into OCD Mode, even if the MM bit is set. This allows Monitor Mode

programs to be debugged.

9.2.3

OCD Mode

If the Monitor Mode (MM) bit in the Development Control register (DC) is cleared, the CPU will

enter Debug Mode in OCD Mode. When the CPU is in OCD Mode, the Debug Status (DBS) bit

in the Development Status (DS) register is set, in addition to the D bit in SR in the CPU. OCD

Mode is similar to Monitor Mode, except that instructions are fetched from the OCD system.

OCD instructions are loaded by the debug tool by writing the opcode to the Debug Instruction

tion Complete bit in DS (DS:INC) will be cleared until the CPU has completed the operation. The

CPU is then halted until DINST is written again.

The first instruction entered must be aligned to the MSB of DINST. A sequence of instructions

can be entered to DINST one word at a time, in the same sequence they would appear in pro-

gram memory, i.e. they do not need to be word aligned. If the upper halfword of an extended

instruction is written to the lower halfword of DINST, the lower halfword of the instruction is writ-

ten as the upper halfword of DINST in the next access. If the last instruction in a sequence is

written to the upper halfword of DINST, the lower halfword should be written with a nop opcode.

See Figure 9-3 for an illustration of a sequence of operations used to execute instructions in

OCD Mode.

Any instruction valid in Monitor Mode is also valid in OCD Mode. Memory operations can be con-

ducted without any special synchronization with external hardware.

All OCD units can be configured while the CPU executes in OCD Mode, but the following debug

features are disabled:

• PC breakpoints

• Data breakpoints

• Watchpoints

• Program Trace

• Data Trace

• Nano Trace

OCD Mode is exited by writing the retd instruction to DINST.

AVR32AP Datasheet(PDF) 92 Page - ATMEL Corporation

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