AVR32AP datasheet(51/181 Pages) ATMEL

51 / 181 page

32001A–AVR32–06/06

AVR32

the same physical address. In other words, the Virtual Page Number (VPN) section of the virtual

address uniquely specifies the Physical Frame Number (PFN) section in the physical address.

In private virtual memory, each process has its own virtual memory space. This is implemented

by using both the VPN and the Application Space Identifier (ASID) of the current process when

searching the TLB for a match. Each process has a unique ASID. Therefore, two different pro-

cesses accessing the same VPN won’t hit the same TLB entry, since their ASID is different.

Pages can be shared between processes in private virtual mode by setting the Global (G) bit in

the page table entry. This will disable the ASID check in the TLB search, causing the VPN sec-

tion uniquely to identify the PFN for the particular page.

4.2.2

MMU interface registers

The following registers are used to control the MMU, and provide the interface between the

MMU and the operating system. Most registers can be altered both by the application software

(by writing to them) and by hardware when an exception occurs. All the registers are mapped

into the System Register space, their addresses are presented in Section 2.5 ”System registers”

on page 10. The MMU interface registers are shown in Figure 4-3 on page 52.

AVR32AP Datasheet(PDF) 51 Page - ATMEL Corporation