AVR32AP datasheet(22/181 Pages) ATMEL

22 / 181 page

32001A–AVR32–06/06

AVR32

prefetch unit will remove the change-of-flow instruction from the pipeline and replace it with the

target instruction. This is called branch folding.

In Java mode, the prefetch unit is able to recognize certain Java instruction pairs and merge

them together to one merged instruction. These merged instructions are passed on to ID as one

instruction.

Details about the prefetch unit is given in chapter 5.

3.3

Decode unit

The decode unit generates the necessary signals in order for the instruction to execute correctly.

The ID stage accepts one instruction each clock cycle from the prefetch unit. This instruction is

then decoded, and control signals and register file addresses are generated. If the instruction

cannot be decoded, an illegal instruction or unimplemented instruction exception is issued. The

ID stage also contains a state machine required for controlling multicycle instructions.

The ID stage performs the remapping of register file addresses from logical to physical

addresses. This is used both for remapping register address into the different contexts, and for

remapping registers to the Java operand stack if the R bit in the status register is set. The ID

stage also contains the Java Operand Stack Pointer (JOSP) register which is used to address

the Java operand stack if the CPU is running in Java mode.

The IS stage performs register file reads and keeps track of data hazards in the pipeline. If haz-

ards exist, pipelines are frozen as needed in order to resolve the hazard.

3.4

ALU pipeline

The ALU pipeline performs most of the data manipulation instructions, like arithmetical and logi-

cal operations. The A1 stage performs the following tasks:

• Target address calculation and condition check for change-of-flow instructions. The A1

pipestage checks if the branch prediction performed by the prefetch unit was correct. If not,

the prefetch unit is notified so that the pipeline can be flushed, the correct instruction can be

fetched and the BTB can be updated.

• Condition code checking for conditional instructions.

• Address calculation for indexed memory accesses

• Writeback address calculation for the LS pipeline.

• All flag setting for arithmetical and logical instructions.

• The A2 stage performs the following tasks:

• The saturation needed by satadd and satsub.

• The operation and flag setting needed by satrnds, satrndu, sats and satu.

AVR32AP Datasheet(PDF) 22 Page - ATMEL Corporation