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AVR32AP Datasheet(PDF) 72 Page - ATMEL Corporation |
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AVR32AP Datasheet(HTML) 72 Page - ATMEL Corporation |
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72 / 181 page  72 32001A–AVR32–06/06 AVR32 Example: Mov R0, 0 cache DCACHE_FLUSH, R0[DCACHE_CLEAN_ALL] sync 0 cache ICACHE_FLUSH, R0[ICACHE_INVALIDATE_ALL] mov PC, new_code_label 6.4 Debug access to ICache memories It is possible to directly access the memories in the ICache through the SAB bus. The ICache maps read or write requests to the cache memories by decoding the address as shown below: Figure 6-1. ICache direct access addressing. Note that the ICache only supports word-aligned 32-bit accesses. Other sizes or alignments may cause undefined behaviour. Table 6-3. ICache direct access address fields Field Size (bits) Description T/D 1 Access tag memories if set, data memories if cleared Way 2 Selects which line in a set to access. Set log2(number of sets) Selects which set to access. Byte 5 Selects which byte of the line to access. Ignored if accessing tag memory. Ignored T/D Way Set Byte 31 0 |
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