AVR32AP datasheet(54/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

4.2.2.3

Page Table Base Register - PTBR

This register points to the start of the page table structure. The register is not used by hardware,

and can only be modified by software. The register is meant to be used by the MMU-related

exception routines.

4.2.2.4

TLB Exception Address Register - TLBEAR

This register contains the virtual address that caused the most recent MMU-related exception.

The register is updated by hardware when such an exception occurs.

4.2.2.5

MMU Control Register - MMUCR

The MMUCR controls the operation of the MMU. The MMUCR has the following fields:

• DRP - Data TLB Replacement Pointer. DRP points to the TLB entry to overwrite when a new

entry is loaded by the tlbw instruction. The DRP field is incremented automatically by

hardware upon every tlbw instruction. If DRP wraps around after such an incrementation,

DRP is set to the value indicated by DLA. The DRP field can also be written by software,

allowing the exception routine to implement a replacement algorithm in software. The DRP

field is 5 bits wide, to support 32 entries in the UTLB.

When a DTLB protection exception, DTLB modified exception, or ITLB protection exception

occurs on a valid page, the DRP is set to the index of that page.

• DLA - Data TLB Lockdown Amount. Specified the number of locked down TLB entries. All

TLB entries from entry 0 to entry (DLA-1) are locked down. If DLA equals zero, no entries are

locked down. A DLA setting does not prevent the programmer from modifying an entry in the

TLB. DLA is only used when the tlbw autoincrement of DRP causes DRP to wrap.

• S - Segmentation Enable. If set, the segmented memory model is used in the translation

process. If cleared, the memory is regarded as unsegmented. The S bit is set after reset.

• N - Not Found. Set if the entry searched for by the TLB Search instruction (tlbs) was not

found in the TLB.

• I - Invalidate. Writing this bit to one invalidates all TLB entries. The bit is always read as zero.

• M - Mode. Selects whether the shared virtual memory mode or the private virtual memory

mode should be used. The M bit determines how the TLB address comparison should be

performed, see Table 4-4.

• E - Enable. If set, the MMU page translation is enabled. If cleared, no page translation is

performed.

4.2.2.6

TLB Accessed Register HI - TLBARHI

TLBARHI is not implemented since only 32 TLB entries are present.

Table 4-4.

MMU mode implied by the M bit

MMode

Private Virtual Memory

Shared Virtual Memory

AVR32AP Datasheet(PDF) 54 Page - ATMEL Corporation

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