AVR32AP datasheet(74/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

Data Cache and Write Buffer

The AVR32 AP uses a data cache and a write buffer in order to increase performance and

reduce power consumption. The data cache has the following features:

• Virtually indexed, physically tagged.

• 4-way set-associative.

• 32-byte line size

• Least recently used allocate-on-read-miss line replacements.

• Synthesizable design using standard single and two port RAMs.

• Lockable on a per-line basis.

• Cacheable or uncacheable operation configurable on a per-page basis through the MMU.

• Write-back or write-through operation configurable on a per-page basis through the MMU.

• All accesses are subject to MMU protection and translation checks.

• Powerful cache maintenance operations, allowing many common cache operations to be

performed through a single instruction.

The number of sets in the data cache is specified in the CONFIG1 register described in chapter

2.6. The total cache size is (number of sets * line size * associativity), i.e. (128 * number of sets)

bytes.

The write buffer has the following features:

• Bufferable or unbufferable writes configurable on a per-page basis through the MMU.

• Does write combining on bufferable writes.

• Holds up to 32 bytes of buffered data, plus up to 32 bytes of data that are about to be written

to the bus.

• Can be manually flushed by using the SYNC instruction.

7.1

Data cache behaviour

Reset invalidates all entries in the DCache.

All reads result in an DCache lookup and will return the cached data if the requested address is

found in the cache (a cache hit). If the address is not found (a cache miss) and the address is in

a cacheable area, a burst read access is started on the system bus in order to read an entire

cache line of data. The read data will be written to an unlocked line according to a round-robin

scheme, possibly replacing another line.

If the cache miss is in an uncacheable area, a single non-sequential read is started on the sys-

tem bus.

All writes result in a DCache lookup and will update the cached data if the requested address is

found in the cache (a cache hit). If the address is not found (a cache miss) or the address is con-

figured as write-through, the write will also update the write buffer (if bufferable) or be written to

the bus (if unbufferable).

If the MMU is disabled or the fetch is from an unmapped segment, the cacheability, bufferability

and write-back/write-through attributes of memory areas are predefined as shown in the archi-

tecture manual. If the MMU is enabled and the access is to a mapped segment, the attributes

are configured through the C, B and W bits in the TLB.

AVR32AP Datasheet(PDF) 74 Page - ATMEL Corporation

AVR32AP Datasheet(HTML) 74 Page - ATMEL Corporation

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