AVR32AP datasheet(32/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

The Mode bits are set correctly to reflect the priority of the accepted event, and the cor-

rect register file banks are selected. The address of the event handler, as shown in

Table 3-2, is loaded into the Program Counter.

The execution of the event routine then continues from the effective address calculated.

The rete instruction signals the end of the event. When encountered, the values in the Return

Status Register and Return Address Register corresponding to the event context are restored to

the Status Register and Program Counter. The restored Status Register contains information

allowing the core to resume operation in the previous execution mode. This concludes the event

handling.

3.10.3

Supervisor calls

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is

designed so that privileged routines can be called from any context. This facilitates sharing of

code between different execution modes. The scall mechanism is designed so that a minimal

execution cycle overhead is experienced when performing supervisor routine calls from time-

critical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behav-

iour is detailed in the Instruction Set Reference in the Architecture Manual. In order to allow the

scall routine to return to the correct context, a return from supervisor call instruction, rets, is

implemented.

3.10.4

Debug requests

The AVR32 architecture defines a dedicated debug mode. When a debug request is received by

the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the

status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the

Debug Exception handler. By default, debug mode executes in the exception context, but with

dedicated Return Address Register and Return Status Register. These dedicated registers

remove the need for storing this data to the system stack, thereby improving debuggability. The

mode bits in the status register can freely be manipulated in Debug mode, to observe registers

in all contexts, while retaining full privileges.

Debug mode is exited by executing the retd instruction. This returns to the previous context.

3.11

Entry points for events

Several different event handler entry points exists. For AVR32B, the reset routine entry address

is always fixed to 0xA000_0000. This address resides in unmapped, uncached space in order to

ensure well-defined resets.

TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-

dler can be placed. This speeds up execution by removing the need for a jump instruction placed

at the program address jumped to by the event hardware. All other exceptions have a dedicated

event routine entry point located relative to EVBA. The handler routine address identifies the

exception source directly.

All external interrupt requests have entry points located at an offset relative to EVBA. This

autovector offset is specified by an external Interrupt Controller. The programmer must make

sure that none of the autovector offsets interfere with the placement of other code. The autovec-

tor offset has 14 address bits, giving an offset of maximum 16384 bytes.

Special considerations should be made when loading EVBA with a pointer. Due to security con-

siderations, the event handlers should be located in the privileged address space, or in a

AVR32AP Datasheet(PDF) 32 Page - ATMEL Corporation

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