AVR32AP datasheet(56/181 Pages) ATMEL

56 / 181 page

32001A–AVR32–06/06

AVR32

The MMU has a 4-entry micro-ITLB, and an 8 entry micro-DTLB connected to the caches. The

caches use the micro-TLBs directly for look-ups. If the desired entry is not found in the small

micro-TLB, the larger common TLB is searched. If the entry is found in the common TLB, it is

copied into the desired micro-TLB and the access is performed. Otherwise, a page miss excep-

tion is issued.

The use of micro-TLBs is completely transparent to the user. Hardware is responsible for replac-

ing entries in the micro-TLB with entries found in the main TLB. Small micro-TLBs are used in

order to increase clock frequency, since performing a look-up in a large TLB is slower than for a

small TLB. If an access misses in the micro-TLB, a clock cycle penalty is imposed for performing

a look-up in the large TLB.

4.2.5

Translation process

The translation process maps addresses from the virtual address space to the physical address

space. The addresses are generated as shown in Table 4-5, depending on the page size

chosen:

Table 4-5.

Physical address generation

Page size

Physical address

1 Kb

PFN[31:10], VA[9:0]

4 Kb

PFN[31:12], VA[11:0]

64 Kb

PFN[31:16], VA[15:0]

1 Mb

PFN[31:20], VA[19:0]

AVR32AP Datasheet(PDF) 56 Page - ATMEL Corporation