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AVR32AP Datasheet(PDF) 77 Page - ATMEL Corporation

Part # AVR32AP
Description  32-bit AVR Microcontroller
PDF  181 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AVR32AP Datasheet(HTML) 77 Page - ATMEL Corporation

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77
32001A–AVR32–06/06
AVR32
as clean. If the write buffer is full the instruction will stall. If the line is not found or the line is
clean, nothing is done. If any MMU exceptions happen, the operation is silently aborted.
7.3.7
Clean & Invalidate
This operation performs a clean (as described in chapter 7.3.6) and then a invalidate (as
described in chapter 7.3.5).
7.4
Prefetch instruction
The prefetch operation will try to load the line containing the address given by the parameter into
the cache. If the line exists in the cache, nothing is done. If the line does not exist in the cache, it
will be fetched from the bus - even if the area is uncacheable. If any MMU exceptions happen,
the operation is silently aborted.
7.5
Sync instructions
The sync instruction will flush the write buffer, by forcing it to write any dirty data to the bus. This
can be used to ensure the data in main memory is consistent.
It will also ensure all pending read operations are completed, so e.g. invalidate and unlock oper-
ations are guaranteed to complete correctly.
7.6
Memory mapped cache memories
Both the data and tag memories of the DCache are mapped into the global address space, and
can be accessed by programs or through the SAP or OCD system. This can be used for com-
plex cache control, or simply as a very fast scratch RAM. The base address of the memory map
is IMPLEMENTATION DEFINED, but will always be in an unmapped privileged segment. The
size of the memory mapped area is always twice the cache size.
This mapped area is not available through the instruction cache or from peripherals, so it is not
possible to run programs from this area, or DMA data to or from it.
Note: Incorrect values written to the memory mapped cache memories may cause data corrup-
tion or unpredictable behaviour.
The DCache maps read or write requests to the cache memories by decoding the address as
shown below:
Figure 7-1.
DCache direct access addressing.
Base
T/D
Way
Set
Byte
31
0



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