AVR32AP datasheet(82/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

8.3

Connecting coprocessors to the TCB bus

Connecting new coprocessors to the TCB bus is simple. Just assert the bit number in

tcb_present corresponding to the desired coprocessor number, and AND the tcb_ready,

tcb_rdataa and tcb_rdatab signals from the coprocessor together with the same signals from the

other coprocessors. The TCB signals output from the CPU must also be routed to the corre-

sponding inputs on the coprocessor.

8.4

Execution of coprocessor instructions

All coprocessor instructions flow through the LS pipeline. The state machine in the DA stage is

responsible for correct execution of the coprocessor instructions. The coprocessor data transfer

instructions behave very similarly to their corresponding load/store instructions. The main differ-

ence is that data is written/read from the TCB bus instead of the integer register file. The timing

tcb_ready

Acknowledge signal from the coprocessor slaves. Indicates if the

coprocessor or system register was able to process the command from

the master. If not, the LS pipeline should stall until the tcb_ready signal

is asserted. Each slave connected to the TCB has an individual ready

signal, and all these are AND-ed together to form tcb_ready. All slaves

connected to the TCB should therefore leave their ready signal HIGH

AT ALL TIMES unless they really want to stall the TCB. If one or more

slaves drive their ready signal low, the TCB and LS pipe is stalled.

A TCB slave may only start a stall during the address phase of the TCB

operation. If tcb_ready stays asserted on the first clock edge after the

operation is initiated, tcb_ready must stay asserted until the data is

ready.

tcb_present[7:0]

Indicates which coprocessors are present on the TCB bus. AVR32

supports 8 coprocessors, and each of the 8 coprocessor addresses is

either in use by a coprocessor or not in use. When attaching a

coprocessor on the TCB bus, the system integrator must assert the

corresponding bit position in the tcb_present bus to 1. The bit position

of unconnected TCB addresses must be disasserted. The tcb_present

bus is used by the ID stage when decoding a coprocessor instruction,

in order to detect whether a coprocessor absent exception should be

triggered.

The tcb_present signal is static, ie. it should not change during

execution.

If bit n asserted, coprocessor n is present. Otherwise, no coprocessor

with address n is present on the TCB bus.

tcb_rdataa[31:0]

tcb_rdatab[31:0]

Data read from the coprocessor to the CPU. The supported data widths

are word and doubleword. Each slave connected to the TCB has

individual tcb_rdataa and tcb_rdatab outputs, and all these are AND-ed

together to form the tcb_rdataa and tcb_rdatab that is input to the CPU.

All slaves connected to the TCB should therefore leave their

tcb_rdataa and tcb_rdatab outputs HIGH AT ALL TIMES unless they

really want to perform a write to the TCB.

For word transfers, tcb_rdataa contains the data to transfer, and

tcb_rdatab is UNDEFINED. For doubleword transfers, tcb_rdataa

contains the most significant part of the data, and tcb_rdatab contains

the least significant part of the data.

Table 8-1.

TCB signals

Name

Dir

Description

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