AMD-K6-2ESLASH233AMZ datasheet(265/332 Pages) AMD

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Chapter 13

Clock Control

247

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Clock Control

13.1

Clock Control States

The AMD-K6-2E processor supports five modes of clock control.

The processor can transition between these modes to maximize

performance, to minimize power dissipation, or to provide a

balance between performance and power. (See “Power

Dissipation” on page 258 for the maximum power dissipation of

the AMD-K 6 -2 E processor w i thi n the normal and the

reduced-power states.)

The five clock-control states supported are:

Normal State—The processor is running in real mode,

virtual-8086 mode, protected mode, or system management

mode (SMM). In this state, all clocks are running— including

the external bus clock, CLK, and the internal processor

clock—and the full features and functions of the processor

are available.

Halt State—This low-power state is entered following the

successful execution of the HLT instruction. During this

state, the internal processor clock is stopped.

Stop Grant State—This low-power state is entered following

the recognition of the assertion of the STPCLK# signal.

During this state, the internal processor clock is stopped.

Stop Grant Inquire State—This state is entered from the

Halt state and the Stop Grant state as the result of a

system-initiated inquire cycle.

Stop Clock State—This low-power state is entered from the

Stop Grant state when the CLK signal is stopped.

Figure 87 on page 248 illustrates the clock control state

transitions. Each of the four reduced-power states are described

in the following sections.

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