AMD-K6-2ESLASH233AMZ datasheet(262/332 Pages) AMD

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Test and Debug

Chapter 12

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

enabled (bit 3 of CR4 is 1), any attempt to load DR5 or DR4

results in an undefined opcode exception. Likewise, any

attempt to store DR5 or DR4 also results in an undefined

opcode exception.

DR6. If a breakpoint is enabled in DR7, and the breakpoint

conditions as defined in DR7 occur, then the corresponding B

bit (B3–B0) in DR6 is set to 1. In addition, any other breakpoints

defined using these particular breakpoint conditions are

reported by the processor by setting the appropriate B bits in

DR6, regardless of whether these breakpoints are enabled or

disabled. However, if a breakpoint is not enabled, a debug

exception does not occur for that breakpoint.

If the processor decodes an instruction that writes or reads DR7

through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in

DR7) and the processor generates a debug exception. This

operation allows control to pass to the debugger prior to debug

If the Trap Flag (bit 8) of the EFLAGS register is 1, the

processor generates a debug exception after the successful

execution of every instruction (single-step operation) and sets

the BS bit (bit 14) in DR6 to indicate the source of the

exception.

When the processor switches to a new task and the debug trap

bit (T bit) in the corresponding Task State Segment (TSS) is 1,

the processor sets the BT bit (bit 15) in DR6 and generates a

debug exception.

DR7. When set to 1, L3–L0 locally enable breakpoints 3 through

0, respectively. L3–L0 are cleared to 0 whenever the processor

executes a task switch. Clearing L3–L0 to 0 disables the

breakpoints and ensures that these particular debug exceptions

are only generated for a specific task.

When set to 1, G3–G0 globally enable breakpoints 3 through 0,

respectively. Unlike L3–L0, G3–G0 are not cleared to 0

whenever the processor executes a task switch. Not clearing

G3–G0 to 0 allows breakpoints to remain enabled across all

tasks. If a breakpoint is enabled globally but disabled locally,

the global enable overrides the local enable.

AMD-K6-2E/233AMZ Datasheet(PDF) 262 Page - Advanced Micro Devices

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