AMD-K6-2ESLASH233AMZ datasheet(108/332 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.7

AP (Address Parity)

Pin Attribute

Bidirectional

Pin Location

AK-02

Summary

AP contains the even parity bit for cache line addresses driven

and sampled on A[31:5]. Even parity means that the total

number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not

used for the generation or checking of address parity because

these bits are not required to address a cache line.) AP is driven

by the processor during processor-initiated cycles and is

sampled by the processor during inquire cycles. If AP does not

reflect even parity during an inquire cycle, the processor

asserts APCHK # to indicate an address bus parity check. The

processor does not take an internal exception as the result of

detecting an address bus parity check, and system logic must

respond appropriately to the assertion of this signal.

Driven, Sampled, and

Floated

As an Output: The processor drives AP valid off the clock edge

on which ADS# is asserted until the clock edge on which NA# or

the last expected BRDY# of the cycle is sampled asserted. AP is

driven during memory cycles, I/O cycles, special bus cycles, and

interrupt acknowledge cycles. The processor continues to drive

AP while the bus is idle.

As an Input: The processor samples AP during inquire cycles on

the clock edge on which EADS# is sampled asserted.

The processor floats AP off the clock edge that AHOLD or

BOFF # is sampled asserted and off the clock edge that the

processor asserts HLDA in recognition of HOLD.

The processor resumes driving AP off the clock edge on which

the processor samples AHOLD or BOFF # negated and off the

clock edge on which the processor negates HLDA.

AMD-K6-2E/233AMZ Datasheet(PDF) 108 Page - Advanced Micro Devices