AMD-K6-2ESLASH233AMZ datasheet(112/332 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.11

BOFF# (Backoff)

Pin Attribute

Input

Pin Location

Z-04

Summary

If BOFF # is sampled asserted, the processor unconditionally

aborts any cycles in progress and transitions to a bus hold state

by floating the following signals: A[31:3], ADS #, ADSC #, AP,

BE[7:0]#, CACHE #, D[63:0], D/C #, DP[7:0], LOCK #, M/IO #,

PCD, PWT, SCYC, and W/R#. These signals remain floated until

BOFF# is sampled negated. This allows an alternate bus master

or the system to control the bus.

When BOFF# is sampled negated, any processor cycle that was

aborted due to the assertion of BOFF # is restarted from the

beginning of the cycle, regardless of the number of transfers

that were completed. If BOFF# is sampled asserted on the same

clock edge as BRDY # of a bus cycle of any length, then BOFF #

takes precedence over the BRDY #. In this case, the cycle is

aborted and restarted after BOFF# is sampled negated.

Sampled

BOFF# is sampled on every clock edge. The processor floats its

bus signals off the clock edge on which BOFF # is sampled

asserted. These signals remain floated until the clock edge on

which BOFF# is sampled negated.

BOFF # is recognized while INIT and RESET are sampled

asserted.

AMD-K6-2E/233AMZ Datasheet(PDF) 112 Page - Advanced Micro Devices