AMD-K6-2ESLASH233AMZ datasheet(113/332 Pages) AMD

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Chapter 5

Signal Descriptions

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

5.12

BRDY# (Burst Ready)

Pin Attribute

Input, Internal Pullup

Pin Location

X-04

Summary

BRDY # is asserted to the processor by system logic to indicate

either that the data bus is being driven with valid data during a

read cycle or that the data bus has been latched during a write

cycle. If necessary, the system logic can insert bus cycle wait

states by negating BRDY# until it is ready to continue the data

transfer. BRDY # is also used to indicate the completion of

special bus cycles.

Sampled

BRDY# is sampled every clock edge within a bus cycle starting

with the clock edge after the clock edge that negates ADS #.

BRDY # is ignored while the bus is idle. The processor samples

the following inputs on the clock edge on which BRDY # is

sampled asserted: D[63:0], DP[7:0], and KEN # during read

cycles, EWBE # during write cycles (if not masked off), and

WB/WT # during read and write cycles. If NA # is sampled

asserted prior to BRDY#, then KEN# and WB/WT# are sampled

on the clock edge on which NA# is sampled asserted.

The number of times the processor expects to sample BRDY #

asserted depends on the type of bus cycle, as follows:

One time for a single-transfer cycle, a special bus cycle, or

each of two cycles in an interrupt acknowledge sequence

Four times for a burst cycle (once for each data transfer)

BRDY # can be held asserted for four consecutive clocks

throughout the four transfers of the burst, or it can be negated

to insert wait states.

AMD-K6-2E/233AMZ Datasheet(PDF) 113 Page - Advanced Micro Devices