AMD-K6-2ESLASH233AMZ datasheet(135/332 Pages) AMD

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Chapter 5

Signal Descriptions

117

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

5.39

PWT (Page Writethrough)

Pin Attribute

Output

Pin Location

AL-03

Summary

The processor drives PWT to indicate the operating system’s

specification of the writeback state or writethrough state for

the page being addressed. PWT, together with WB/WT#,

specifies the data cache-line state during cacheable read misses

and write hits to shared cache lines. See “WB/WT# (Writeback

or Writethrough)” on page 129 for more details.

The state of PWT depends upon the processor’s operating mode

and the state of certain bits in its control registers and TLB as

follows:

In real mode, or in protected and virtual-8086 modes while

paging is disabled (PG bit in CR0 is 0):

PWT output = 0 (writeback state)

In protected and virtual-8086 modes while paging is enabled

(PG bit in CR0 is 1):

•

For accesses to I/O space, page directory entries, and

other non-paged accesses:

PWT output = PWT bit in CR3

•

For accesses to 4-Kbyte page table entries or 4-Mbyte

pages:

PWT output = PWT bit in page directory entry

•

For accesses to 4-Kbyte pages:

PWT output = PWT bit in page table entry

Driven and Floated

PWT is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted.

PWT is floated off the clock edge on which BOFF# is sampled

asserted and off the clock edge on which the processor asserts

HLDA in response to HOLD.

AMD-K6-2E/233AMZ Datasheet(PDF) 135 Page - Advanced Micro Devices

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