| Electronic Components Datasheet Search |
|
AMD-K6-2E/233AMZ Datasheet(PDF) 136 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AMD-K6-2E/233AMZ Datasheet(HTML) 136 Page - Advanced Micro Devices |
|
136 / 332 page ![]() 118 Signal Descriptions Chapter 5 AMD-K6™-2E Processor Data Sheet 22529B/0—January 2000 Preliminary Information 5.40 RESET (Reset) Pin Attribute Input Pin Location AK-20 Summary When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the MMX state, the 3DNow! state, and all registers, and then the processor jumps to address FFFF_FFF0h to start instruction execution. The FLUSH# signal is sampled during the falling transition of RESET to invoke the three-state test mode. Sampled RESET is sampled as a level-sensitive input on every clock edge. System logic can drive the signal either synchronously or asynchronously. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |