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MC68HC908GR4MP Datasheet(PDF) 206 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP Datasheet(HTML) 206 Page - Freescale Semiconductor, Inc |
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206 / 286 page  Serial Peripheral Interface (SPI) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 206 Freescale Semiconductor 20.3 Pin Name Conventions and I/O Register Addresses The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 20-1. The generic pin names appear in the text that follows. 20.4 Functional Description Figure 20-1 summarizes the SPI I/O registers and Figure 20-2 shows the structure of the SPI module. The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt-driven. If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. See 16.5.3 Port D Input Pullup Enable Register. The following paragraphs describe the operation of the SPI module. Table 20-1. Pin Name Conventions SPI Generic Pin Names: MISO MOSI SS SPSCK CGND Full SPI Pin Names: SPI PTD1/ATD9 PTD2/ATD10 PTD0/ATD8 PTD3/ATD11 VSS Addr. Register Name Bit 7 654321 Bit 0 $0010 SPI Control Register (SPCR) Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write: Reset: 00101000 $0011 SPI Status and Control Register (SPSCR) Read: SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0 Write: Reset: 00001000 $0012 SPI Data Register (SPDR) Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset = Unimplemented R = Reserved Figure 20-1. SPI I/O Register Summary |
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