MC68HC908GR4MP datasheet(202/286 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

202

Freescale Semiconductor

BW — SIM Break Wait

Clear BW by writing a 0 to it. Reset clears BW. BW can be read within the break state SWI routine.

The user can modify the return address on the stack by subtracting one from it.

1 = Wait mode was exited by break interrupt.

0 = Wait mode was not exited by break interrupt.

19.7.2 SIM Reset Status Register

The SRSR register contains flags that show the source of the last reset. The status register will

automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the

reset source can be flagged at any time depending on the conditions at the time of the internal or external

reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

PIN — External Reset Bit

1 = Last reset caused by external reset pin (RST)

0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter

0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

MODRST — Monitor Mode Entry Module Reset Bit

1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after

POR while IRQ = VDD

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset caused by the LVI circuit

0 = POR or read of SRSR

Address:

$FE01

Bit 7

654321

Bit 0

Read:

POR

COP

ILOP

ILAD

MODRST

LVI

Write:

Reset:

10000000

= Unimplemented

Figure 19-21. SIM Reset Status Register (SRSR)

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