MC68HC908GR4MP datasheet(199/286 Pages) FREESCALE

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Low-Power Modes

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

199

19.5.4 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The

user can select whether flags are protected from being cleared by properly initializing the break clear flag

enable bit (BCFE) in the SIM break flag control register (SBFCR).

Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This

protection allows registers to be freely read and written during break mode without losing status flag

information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains

cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,

a read of one register followed by the read or write of another — are protected, even when the first step

is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step

will clear the flag as normal.

19.6 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby

situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is

described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition

code register, allowing interrupts to occur.

19.6.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 19-15 shows

the timing for wait mode entry.

A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.

Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.

In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the

module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

Wait mode also can be exited by a reset or break in emulation mode. A break interrupt during wait mode

sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit,

COPD, in the CONFIG register is 0, then the computer operating properly module (COP) is enabled and

remains active in wait mode.

Figure 19-15. Wait Mode Entry Timing

WAIT ADDR + 1

SAME

IAB

IDB

PREVIOUS DATA

NEXT OPCODE

SAME

WAIT ADDR

SAME

R/W

Note:

Previous data can be operand data or the WAIT opcode, depending on the

last instruction.

MC68HC908GR4MP Datasheet(PDF) 199 Page - Freescale Semiconductor, Inc

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