MC68HC908GR4MP datasheet(208/286 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

208

Freescale Semiconductor

20.4.1 Master Mode

The SPI operates in master mode when the SPI master bit, SPMSTR, is set.

NOTE

Configure the SPI modules as master or slave before enabling them.

Enable the master SPI before enabling the slave SPI. Disable the slave SPI

before disabling the master SPI. See 20.13.1 SPI Control Register.

Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI

module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers

to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI

pin under the control of the serial clock. See Figure 20-3.

Figure 20-3. Full-Duplex Master-Slave Connections

The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.

See 20.13.2 SPI Status and Control Register. Through the SPSCK pin, the baud rate generator of the

master also controls the shift register of the slave peripheral.

As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s

MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that

SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,

SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control

SPTE bit.

20.4.2 Slave Mode

The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input

for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI

must be at logic 0. SS must remain low until the transmission is complete. See 20.7.2 Mode Fault Error.

In a slave SPI module, data enters the shift register under the control of the serial clock from the master

SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,

and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data

The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is

twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for

an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only

SHIFT REGISTER

BAUD RATE

GENERATOR

MASTER MCU

SLAVE MCU

VDD

MOSI

MISO

SPSCK

MC68HC908GR4MP Datasheet(PDF) 208 Page - Freescale Semiconductor, Inc

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