MC68HC908GR4MP datasheet(211/286 Pages) FREESCALE

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Transmission Formats

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

211

slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected

slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS

pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. See

20.7.2 Mode Fault Error. When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK

edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can

remain low between transmissions. This format may be preferable in systems having only one master and

only one slave driving the MISO data line.

Figure 20-6. Transmission Format (CPHA = 1)

When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This

causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the

transmission begins, no new data is allowed into the shift register from the transmit data register.

Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of

SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the

shift register after the current transmission.

20.5.4 Transmission Initiation Latency

When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA

has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK

signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.

When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its

active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and

the start of the SPI transmission. See Figure 20-7. The internal SPI clock in the master is a free-running

derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and

SPMSTR bits are set. Since the SPI clock is free-running, it is uncertain where the write to the SPDR

occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown

in Figure 20-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU

bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus

cycles for DIV128.

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

123

SPSCK CYCLE #

FOR REFERENCE

SPSCK; CPOL = 0

SPSCK; CPOL =1

MOSI

FROM MASTER

MISO

FROM SLAVE

SS; TO SLAVE

CAPTURE STROBE

MC68HC908GR4MP Datasheet(PDF) 211 Page - Freescale Semiconductor, Inc

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