MC68HC908GR4MP datasheet(209/286 Pages) FREESCALE

209 / 286 page

Transmission Formats

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

209

controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency

of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.

When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the

MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its

transmit data register. The slave must write to its transmit data register at least one bus cycle before the

master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the

MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of

the transmission.

When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is

clear, the falling edge of SS starts a transmission. See 20.5 Transmission Formats.

NOTE

SPSCK must be in the proper idle state before the slave is enabled to

prevent SPSCK from appearing as a clock edge.

20.5 Transmission Formats

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted

in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select

line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere

with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate

multiple-master bus contention.

20.5.1 Clock Phase and Polarity Controls

Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits

in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects

an active high or low clock and has no significant effect on the transmission format.

The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The

clock phase and polarity should be identical for the master SPI device and the communicating slave

device. In some cases, the phase and polarity are changed between transmissions to allow a master

device to communicate with peripheral slaves having different requirements.

NOTE

Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing

the SPI enable bit (SPE).

20.5.2 Transmission Format When CPHA = 0

Figure 20-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a

replacement for data sheet parametric information.

MC68HC908GR4MP Datasheet(PDF) 209 Page - Freescale Semiconductor, Inc