MC68HC908GR4MP datasheet(118/286 Pages) FREESCALE

118 / 286 page

External Interrupt (IRQ)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

118

Freescale Semiconductor

Figure 12-1. IRQ Module Block Diagram

When an interrupt pin is both falling-edge and low-level-triggered, the interrupt remains set until both of

the following occur:

•

Vector fetch or software clear

•

Return of the interrupt pin to high level

The vector fetch or software clear may occur before or after the interrupt pin returns to high level. As long

as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control

bit, thereby clearing the interrupt even if the pin stays low.

When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request

is not presented to the interrupt priority logic unless the IMASK bit is clear.

NOTE

The interrupt mask (I) in the condition code register (CCR) masks all

interrupt requests, including external interrupt requests.

Addr.

Bit 7

654321

Bit 0

$001D

IRQ Status and Control

Read:

0000

IRQF

IMASK

MODE

Write:

ACK

Reset:

00000000

= Unimplemented

Figure 12-2. IRQ I/O Register Summary

IRQ

ACK

IMASK

CLR

IRQ

HIGH

INTERRUPT

TO MODE

SELECT

LOGIC

IRQ

REQUEST

VDD

MODE

VOLTAGE

DETECT

SYNCHRO-

NIZER

IRQF

TO CPU FOR

BIL/BIH

INSTRUCTIONS

VECTOR

FETCH

DECODER

RESET

VDD

INTERNAL

PULLUP

DEVICE

MC68HC908GR4MP Datasheet(PDF) 118 Page - Freescale Semiconductor, Inc

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