MC68HC908GR4MP datasheet(119/286 Pages) FREESCALE

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IRQ Pin

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

119

12.4 IRQ Pin

A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software

clear, or reset clears the IRQ latch.

If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,

both of the following actions must occur to clear IRQ:

•

Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear

the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in

the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the

IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an

interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not

affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit

another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter

with the vector address at locations $FFFA and $FFFB.

•

Return of the IRQ pin to a high level — As long as the IRQ pin is at a low level, IRQ remains active.

The vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.

The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the latch and the

MODE control bit, thereby clearing the interrupt even if the pin stays low.

If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or

software clear immediately clears the IRQ latch.

The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not

affected by the IMASK bit, which makes it useful in applications where polling is preferred.

Use the BIH or BIL instruction to read the logic level on the IRQ pin.

NOTE

When using the level-sensitive interrupt trigger, avoid false interrupts by

masking interrupt requests in the interrupt routine.

12.5 IRQ Module During Break Interrupts

The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during

the break state. See Chapter 6 Break Module (BRK).

To allow software to clear the IRQ latch during a break interrupt, write a 1 to the BCFE bit. If a latch is

cleared during the break state, it remains cleared when the MCU exits the break state.

To protect CPU interrupt flags during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default

state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on

the IRQ interrupt flags.

MC68HC908GR4MP Datasheet(PDF) 119 Page - Freescale Semiconductor, Inc