MC68HC908GR4MP datasheet(146/286 Pages) FREESCALE

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Input/Output Ports (I/O)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

146

Freescale Semiconductor

16.2 Port A

Port A is an 4-bit special-function port that shares all four of its pins with the keyboard interrupt (KBI)

module. Port A also has software configurable pullup devices if configured as an input port.

16.2.1 Port A Data Register

The port A data register (PTA) contains a data latch for each of the four port A pins.

PTA3–PTA0 — Port A Data Bits

These read/write bits are software programmable. Data direction of each port A pin is under the control

of the corresponding bit in data direction register A. Reset has no effect on port A data.

KBD3–KBD0 — Keyboard Inputs

The keyboard interrupt enable bits, KBIE3–KBIE0, in the keyboard interrupt control register (KBICR)

enable the port A pins as external interrupt pins. See Chapter 13 Keyboard Interrupt (KBI).

16.2.2 Data Direction Register A

Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1

to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.

DDRA3–DDRA0 — Data Direction Register A Bits

These read/write bits control port A data direction. Reset clears DDRA3–DDRA0, configuring all port

A pins as inputs.

1 = Corresponding port A pin configured as output

0 = Corresponding port A pin configured as input

NOTE

Avoid glitches on port A pins by writing to the port A data register before

changing data direction register A bits from 0 to 1.

Figure 16-4 shows the port A I/O logic.

Address:

$0000

Bit 7

4321

Bit 0

Read:

PTA3

PTA2

PTA1

PTA0

Write:

Reset:

Unaffected by reset

Alternative Function:

KBD3

KBD2

KBD1

KBD0

= Unimplemented

Figure 16-2. Port A Data Register (PTA)

Address:

$0004

Bit 7

654321

Bit 0

Read:

0000

DDRA3

DDRA2

DDRA1

DDRA0

Write:

Reset:

00000000

= Unimplemented

Figure 16-3. Data Direction Register A (DDRA)

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