MC68HC908GR4MP datasheet(147/286 Pages) FREESCALE

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Port A

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

147

Figure 16-4. Port A I/O Circuit

When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,

reading address $0000 reads the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-2 summarizes the operation of the port A pins.

16.2.3 Port A Input Pullup Enable Register

The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each

of the four port A pins. Each bit is individually configurable and requires that the data direction register,

DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port

bit’s DDRA is configured for output mode.

Table 16-2. Port A Pin Functions

PTAPUE Bit

DDRA Bit

PTA Bit

I/O Pin Mode

Accesses to DDRA

Accesses to PTA

Read/Write

Read

Write

X(1)

Input, VDD

(4)

DDRA3–DDRA0

PTA3–PTA0(3)

Input, Hi-Z(2)

DDRA3–DDRA0

PTA3–PTA0(3)

Output

DDRA3–DDRA0

PTA3–PTA0

NOTES:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

4. I/O pin pulled up to VDD by internal pullup device

READ DDRA ($0004)

WRITE DDRA ($0004)

RESET

WRITE PTA ($0000)

READ PTA ($0000)

PTAx

DDRAx

PTAx

VDD

PTAPUEx

INTERNAL

PULLUP

DEVICE

MC68HC908GR4MP Datasheet(PDF) 147 Page - Freescale Semiconductor, Inc

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