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MC68HC908GR4MP Datasheet(PDF) 188 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP Datasheet(HTML) 188 Page - Freescale Semiconductor, Inc |
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188 / 286 page ![]() System Integration Module (SIM) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 188 Freescale Semiconductor Figure 19-1. SIM Block Diagram Addr. Register Name Bit 7 654321 Bit 0 $FE00 SIM Break Status Register (SBSR) Read: RRRRRR SBSW R Write: NOTE Reset: 00000000 Note: Writing a logic 0 clears SBSW. $FE01 SIM Reset Status Register (SRSR) Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: POR: 10000000 $FE03 SIM Break Flag Control Reg- ister (SBFCR) Read: BCFE RRRRRRR Write: Reset: 0 = Unimplemented Figure 19-2. SIM I/O Register Summary STOP/WAIT CLOCK CONTROL CLOCK GENERATORS POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS MASTER RESET CONTROL RESET PIN LOGIC LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE RESET CONTROL SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) ÷ 2 VDD INTERNAL PULLUP DEVICE |
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