MC68HC908GR4MP datasheet(191/286 Pages) FREESCALE

191 / 286 page

Reset and System Initialization

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

191

Figure 19-4. External Reset Timing

19.3.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of

external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles

at which point the reset vector will be fetched. See Figure 19-5. An internal reset can be caused by an

illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 19-6.

NOTE

For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles

during which the SIM forces the RST pin low. The internal reset signal then

follows the sequence from the falling edge of RST shown in Figure 19-5.

Figure 19-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.

Figure 19-6. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals and other chips within a system

built around the MCU.

Table 19-2. PIN Bit Set Timing

Reset Recovery

Actual Number of Cycles

POR/LVI

4163 (4096 + 64 + 3)

All others

67 (64 + 3)

RST

IAB

VECT H

VECT L

CGMOUT

IRST

RST

RST PULLED LOW BY MCU

IAB

32 CYCLES

VECTOR HIGH

CGMXCLK

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

COPRST

LVI

POR

INTERNAL RESET

MODRST

MC68HC908GR4MP Datasheet(PDF) 191 Page - Freescale Semiconductor, Inc

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