MC68HC908GR4MP datasheet(190/286 Pages) FREESCALE

190 / 286 page

System Integration Module (SIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

190

Freescale Semiconductor

19.2.1 Bus Timing

In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four

or the PLL output (CGMVCLK) divided by four.

19.2.2 Clock Startup from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the

CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR

timeout has completed. The RST pin is driven low by the SIM during this entire period. The bus clocks

start upon completion of the timeout.

19.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter.

The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is

selectable as 4096 or 32 CGMXCLK cycles. See 19.6.2 Stop Mode.

In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.

Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

19.3 Reset and System Initialization

The MCU has these reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly module (COP)

•

Low-voltage inhibit module (LVI)

•

Illegal opcode

•

Illegal address

•

Forced monitor mode entry reset (MODRST)

All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the

internal reset signal (IRST). IRST causes all registers to be returned to their default values and all

modules to be returned to their reset states.

An internal reset clears the SIM counter (see 19.4 SIM Counter), but an external reset does not. Each of

the resets sets a corresponding bit in the SIM reset status register (SRSR). See 19.7 SIM Registers.

19.3.1 External Pin Reset

The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all

processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a

minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset.

See Table 19-2 for details. Figure 19-4 shows the relative timing.

MC68HC908GR4MP Datasheet(PDF) 190 Page - Freescale Semiconductor, Inc

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