MC68HC908GR4MP datasheet(193/286 Pages) FREESCALE

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SIM Counter

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

193

19.3.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP

bit in the SIM reset status register (SRSR) and causes a reset.

If the stop enable bit, STOP, in the CONFIG register is 0, the SIM treats the STOP instruction as an illegal

opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset

sources.

19.3.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the

CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and

resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively

pulls down the RST pin for all internal reset sources.

19.3.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the

LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin

(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK

cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively

pulls down the RST pin for all internal reset sources.

19.3.2.6 Monitor Mode Entry Module Reset (MODRST)

The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is

entered in the condition where the reset vectors are erased ($FF). (See 15.3.1 Entering Monitor Mode.)

When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all

internal reset sources.

19.4 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the

oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as

a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the

clock for the COP module. The SIM counter is 12 bits long.

19.4.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit

asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to

drive the bus clock state machine.

19.4.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After

an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the

CONFIG register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096

CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using crystals with the

OSCSTOPENB bit set. External crystal applications should use the full stop recovery time, that is, with

SSREC cleared.

MC68HC908GR4MP Datasheet(PDF) 193 Page - Freescale Semiconductor, Inc

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