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SST26VF016B-104V/SN Datasheet(PDF) 4 Page - Microchip Technology

Part # SST26VF016B-104V/SN
Description  2.5V/3.0V 16-Mbit Serial Quad I/O™ (SQI™) Flash Memory
PDF  84 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SST26VF016B-104V/SN Datasheet(HTML) 4 Page - Microchip Technology

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SST26VF016B
DS20005262G-page 4
2014-2022 Microchip Technology Inc. and its subsidiaries
2.0
PIN DESCRIPTION
FIGURE 2-1:
PIN DESCRIPTIONS
TABLE 2-1:
PIN DESCRIPTION
Symbol
Pin Name
Functions
CE#
Chip Enable
The device is enabled by a high-to-low transition on CE#. CE# must remain low for
the duration of any command sequence; or in the case of Write operations, for the
command/data input sequence.
SO
Serial Data Output
for SPI mode
Transfer data serially out of the device. Data is shifted out on the falling edge of the
serial clock. SO is the default state after a Power-on Reset.
SIO[3:0]
Serial Data
Input/Output
Transfer commands, addresses or data serially into the device or data out of the
device. Inputs are latched on the rising edge of the serial clock. Data are shifted out
on the falling edge of the serial clock. The Enable Quad I/O (EQIO) command
instruction configures these pins for Quad I/O mode.
WP#
Write-Protect
The WP# is used in conjunction with the WPEN and IOC bits in the Configuration
register to prohibit write operations to the Block Protection register. This pin only
works in SPI, single-bit and dual-bit Read mode.
VSS
Ground
SI
Serial Data Input
for SPI mode
Transfer commands, addresses or data serially into the device. Inputs are latched on
the rising edge of the serial clock. SI is the default state after a Power-on Reset.
SCK
Serial Clock
Provide the timing of the serial interface.
Commands, addresses or input data are latched on the rising edge of the clock input,
while output data are shifted out on the falling edge of the clock input.
HOLD#
Hold
Temporarily stops serial communication with the SPI Flash memory while the device
is selected. This pin only works in SPI, single-bit and dual-bit Read mode and must
be tied high when not in use.
VDD
Power Supply
Provide power supply voltage.
CE#
SO/SIO1
WP#/SIO2
V
V
HOLD/SIO3
SCK
SI/SIO0
1
2
3
4
8
7
6
5
Top View
1
2
3
4
8
7
6
5
CE#
SO/SIO1
WP#/SIO2
V
V
HOLD/SIO3
SCK
SI/SIO0
Top View
1
2
3
4
8
7
6
5
CE#
SO/SIO1
WP#/SIO2
V
Top View
V
HOLD/SIO3
SCK
SI/SIO0
PIN ASSIGNMENT FOR 8-LEAD SOIC
PIN ASSIGNMENT FOR 8-LEAD SOIJ
PIN ASSIGNMENT FOR 8-CONTACT WDFN



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