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SST26VF016B-104V/SN Datasheet(PDF) 12 Page - Microchip Technology |
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SST26VF016B-104V/SN Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 84 page  SST26VF016B DS20005262G-page 12 2014-2022 Microchip Technology Inc. and its subsidiaries 5.0 INSTRUCTIONS Instructions are used to read, write (erase and pro- gram) and configure the SST26VF016B. The complete list of the instructions is provided in Table 5-1. TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF016B Instruction Description Command Cycle(1) Mode Address Cycle(s)(2,3) Dummy Cycle(s)(3) Data Cycle(s)(3) Max Freq(4) SPI SQI Configuration NOP No Operation 00H X X 0 0 0 104 MHz/ 80 MHz RSTEN Reset Enable 66H X X 0 0 0 RST(5) Reset Memory 99H X X 0 0 0 EQIO Enable Quad I/O 38H X 0 0 0 RSTQIO(6) Reset Quad I/O FFH X X 0 0 0 RDSR Read STATUS Register 05H X 0 0 1 to ∞ X 0 1 1 to ∞ WRSR Write STATUS Register 01H X X 0 0 2 RDCR Read Configuration Register 35H X 0 0 1 to ∞ X 0 1 1 to ∞ Read READ Read Memory 03H X 3 0 1 to ∞ 40 MHz High-Speed Read Read Memory at Higher Speed 0BH X 3 3 1 to ∞ 104 MHz/ 80 MHz X 3 1 1 to ∞ SQOR(7) SPI Quad Output Read 6BH X 3 1 1 to ∞ SQIOR(8) SPI Quad I/O Read EBH X 3 3 1 to ∞ SDOR(9) SPI Dual Output Read 3BH X 3 1 1 to ∞ SDIOR(10) SPI Dual I/O Read BBH X 3 1 1 to ∞ 80 MHz SB Set Burst Length C0H X X 0 0 1 104 MHz/ 80 MHz RBSQI SQI Read Burst with Wrap 0CH X 3 3 n to ∞ RBSPI(8) SPI Read Burst with Wrap ECH X 3 3 n to ∞ Note 1: Command cycle is two-clock periods in SQI mode and eight-clock periods in SPI mode. 2: Address bits above the Most Significant bit of each density can be VIL or VIH. 3: Address, Dummy/Mode bits and Data cycles are two-clock periods in SQI and eight-clock periods in SPI mode. 4: The maximum frequency for all instructions is up to 104 MHz from 2.7V to 3.6V and up to 80 MHz from 2.3V to 3.6V unless otherwise noted. For extended temperature (+125°C), the maximum frequency is up to 80 MHz. 5: RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. 6: Device accepts eight-clock command in SPI mode or two-clock command in SQI mode. 7: Data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command. 8: Address, Dummy/Mode bits and data cycles are two-clock periods. IOC bit must be set to ‘1’ before issu- ing the command. 9: Data cycles are four-clock periods. 10: Address, Dummy/Mode bits and Data cycles are four-clock periods. 11: Sector Addresses: Use AMS-A12, remaining address are “don’t care”, but must be set to VIL or VIH. 12: Blocks are 64-Kbyte, 32-Kbyte or 8-Kbyte, depending on location. Block Erase Address: AMS-A16 for 64-Kbyte; AMS-A15 for 32-Kbyte; AMS-A13 for 8-Kbyte. Remaining addresses are “don’t care”, but must be set to VIL or VIH. |
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