SST26VF016B-104VSLASHSN datasheet(41/84 Pages) MICROCHIP

41 / 84 page



2014-2022 Microchip Technology Inc. and its subsidiaries

DS20005262G-page 41

SST26VF016B

5.38 Deep Power-Down

The Deep Power-Down (DPD) instruction puts the

device in the lowest power consumption mode – the

Deep Power-Down mode. The Deep Power-Down

instruction is ignored during an internal write operation.

While the device is in Deep Power-Down mode, all

instructions will be ignored except for the Release

Deep Power-Down instruction.

Enter Deep Power-Down mode by initiating the Deep

Power-Down (DPD) instruction (B9H) while driving CE#

low. CE# must be driven high before executing the DPD

instruction. After CE# is driven high, it requires a delay

of TDPD before the standby current ISB is reduced to

deep power-down current IDPD. See Table 5-7 for Deep

Power-Down timing. If the device is busy performing an

internal erase or program operation, initiating a Deep

Power-Down instruction will not place the device in

Deep Power-Down mode. See Figures 5-47 and for

the DPD instruction sequence.

FIGURE 5-46:

DEEP POWER-DOWN (

DPD) SEQUENCE (SQI)

FIGURE 5-47:

DEEP POWER-DOWN (

DPD) SEQUENCE (SPI)

TABLE 5-7:

DEEP POWER-DOWN

Symbol

Parameter

Min.

Max.

Units

TDPD

CE# High to Deep Power-Down

—

µs

TSBR

CE# High to Standby Mode

—

µs

Note:

MSN= Most Significant Nibble; LSN = Least Significant Nibble

MODE 3

SCK

SIO[3:0]

CE#

MODE 0

MSN

LSN

TDPD

Standby Mode Deep Power-Down Mode

CE#

SCK

01 2 3 4 5 6 7

High-Impedance

MODE 0

MODE 3

MSb

TDPD

Standby Mode Deep Power-Down Mode

SST26VF016B-104V/SN Datasheet(PDF) 41 Page - Microchip Technology

SST26VF016B-104V/SN Datasheet(HTML) 41 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL