SST26VF016B-104VSLASHSN datasheet(7/84 Pages) MICROCHIP

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DS20005262G-page 7

SST26VF016B

4.1.1

INDIVIDUAL BLOCK PROTECTION

SST26VF016B has a Block Protection register which

provides a software mechanism to write-lock the indi-

vidual memory blocks and write-lock and/or read-lock

the individual parameter blocks. The Block Protection

8-Kbyte parameter blocks (write-lock and read-lock),

and one bit each for the remaining 32-Kbyte and

64-Kbyte overlay blocks (write-lock). See Table 5-6 for

address range protected per register bit.

Each bit in the Block Protection register (BPR) can be

written to a ‘1’ (protected) or ‘0’ (unprotected). For the

parameter blocks, the Most Significant bit is for

read-lock and the Least Significant bit is for write-lock.

Read-locking the parameter blocks provides additional

security for sensitive data after retrieval (e.g., after ini-

tial boot). If a block is read-locked, all reads to the block

return data 00H.

The Write Block Protection Register command is a

two-cycle command which requires that Write Enable

(WREN) is executed prior to the Write Block Protection

Unlock command clears all write protection bits in the

Block Protection register.

4.1.2

WRITE PROTECTION LOCK-DOWN

(VOLATILE)

To prevent changes to the Block Protection register,

use the Lock-Down Block Protection Register (LBPR)

command to enable Write Protection Lock-Down. Once

Write Protection Lock-Down is enabled, the Block

Protection register cannot be changed. To avoid

inadvertent lock-down, the WREN command must be

executed prior to the LBPR command.

To reset Write Protection Lock-Down, performing a power

cycle on the device is required. The Write Protection

Lock-Down status may be read from the STATUS register.

4.1.3

WRITE-LOCK LOCK-DOWN

(NONVOLATILE)

The nonvolatile Write-Lock Lock-Down register is an

alternate register that permanently prevents changes

to the block-protect bits. The nonvolatile Write-Lock

Lock-Down register (nVWLDR) is 40-bit wide per

device: one bit each for the eight 8-Kbyte parameter

blocks and one bit each for the remaining 32-Kbyte and

64-Kbyte overlay blocks. See Table 5-6 for address

range protected per register bit.

Writing ‘1’ to any or all of the nVWLDR bits disables the

change mechanism for the corresponding Write-Lock

bit in the BPR and permanently sets this bit to a ‘1’

(protected) state. After this change, both bits will be set

to ‘1’, regardless of the data entered in subsequent

writes to either the nVWLDR or the BPR.

Subsequent writes to the nVWLDR can only alter

available locations that have not been previously

written to a ‘1’. This method provides write protection

for the corresponding memory-array block by

protecting it from future program or erase operations.

Writing a ‘0’ in any location in the nVWLDR has no

effect on either the nVWLDR or the corresponding

Write-Lock bit in the BPR.

Note that if the Block Protection register had been

previously locked down (see

Section 4.1.2 “Write

Protection Lock-Down (Volatile)”), the device must

be power cycled before using the nVWLDR. If the Block

Protection register is locked down and the Write

nVWLDR command is accessed, the command will be

ignored.

4.2

Hardware Write Protection

The hardware Write Protection pin (WP#) is used in

conjunction with the WPEN and IOC bits in the

Configuration register to prohibit write operations to the

Block Protection and Configuration registers. The WP#

pin function only works in SPI single-bit and dual-bit read

mode when the IOC bit in the Configuration register is

set to ‘0’.

The WP# pin function is disabled when the WPEN bit

in the Configuration register is ‘0’. This allows

installation of SST26VF016B in a system with a

grounded WP# pin while still enabling Write to the

Block Protection register. The Lock-Down function of

the Block Protection register supersedes the WP# pin.

See Table 4-1 for Write Protection Lock-Down states.

The factory default setting at power-up of the WPEN bit

is ‘0’, disabling the Write-Protect function of the WP#

after power-up. WPEN is a nonvolatile bit; once the bit

is set to ‘1’, the Write-Protect function of the WP# pin

continues to be enabled after power-up. The WP# pin

only protects the Block Protection register and Config-

uration register from changes. Therefore, if the WP#

pin is set to low before or after a Program or Erase

command or while an internal Write is in progress, it will

have no effect on the Write command.

The IOC bit takes priority over the WPEN bit in the

Configuration register. When the IOC bit is ‘1’, the

function of the WP# pin is disabled and the WPEN bit

serves no function. When the IOC bit is ‘0’ and WPEN

is ‘1’, setting the WP# pin active-low prohibits Write

operations to the Block Protection Register.

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