SST26VF016B-104VSLASHSN datasheet(67/84 Pages) MICROCHIP

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DS20005262G-page 67

SST26VF016B

JEDEC Flash Parameter Table: 3rd DWORD

38H

A4:A0

44H

(1-4-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output

00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input

address phase instruction.

A7:A5

Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode

Bits

010b: 2 dummy clocks (8 mode bits) are needed with a single input

opcode, quad input address and quad output data Fast Read instruction.

39H

A15:A8

EBH

(1-4-4) Fast Read Opcode

Opcode for single input opcode, quad input address and quad output data

Fast Read.

3AH

A20:A16

08H

(1-1-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output

01000b: 8 dummy bits are needed with a single input opcode & address

and quad output data Fast Read instruction.

A23:A21

(1-1-4) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

3BH

A31:A24

6BH

(1-1-4) Fast Read Opcode

Opcode for single input opcode & address and quad output data Fast

Read.

JEDEC Flash Parameter Table: 4th DWORD

3CH

A4:A0

08H

(1-1-2) Fast Read Number of Wait states (dummy clocks) needed

before valid output

01000b: 8 dummy clocks are needed with a single input opcode,

address and dual output data fast read instruction.

A7:A5

(1-1-2) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address

and quad output data Fast Read instruction.

3DH

A15:A8

3BH

(1-1-2) Fast Read Opcode

Opcode for single input opcode & address and dual output data Fast Read.

3EH

A20:A16

80H

(1-2-2) Fast Read Number of Wait states (dummy clocks) needed

before valid output

00010b: 0 clocks of dummy cycle.

A23:A21

(1-2-2) Fast Read Number of Mode Bits (in clocks)

010b: 4 clocks of mode bits are needed.

3FH

A31:A24

BBH

(1-2-2) Fast Read Opcode

Opcode for single input opcode, dual input address and dual output data

Fast Read.

TABLE 11-1:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (4 OF 17)

Address

Bit Address

Data

Comments

Note 1: See Section 11.1 “Mapping Guidance Details” for more detailed mapping information.

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