SST26VF016B-104VSLASHSN datasheet(11/84 Pages) MICROCHIP

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DS20005262G-page 11

SST26VF016B

4.6.1

I/O CONFIGURATION (IOC)

The I/O Configuration (IOC) bit re-configures the I/O

pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the

Configuration register. When IOC bit is ‘0’, the WP# pin

and HOLD# pin are enabled (SPI or Dual Configuration

setup). When IOC bit is set to ‘1’, the SIO2 pin and

SIO3 pin are enabled (SPI Quad I/O Configuration

setup). The IOC bit must be set to ‘1’ before issuing the

following SPI commands: SQOR (6BH), SQIOR (EBH),

RBSPI (ECH) and SPI Quad page program (32H).

Without setting the IOC bit to ‘1’, those SPI commands

are not valid. The I/O configuration bit does not apply

when in SQI mode. The default at power-up is ‘0’.

4.6.2

BLOCK PROTECTION VOLATILITY

STATE (BPNV)

The Block Protection Volatility State bit indicates

whether any block has been permanently locked with

the Nonvolatile Write Lock Lock-Down register

(nVWLDR). When no bits in the nVWLDR have been

set, the BPNV is ‘1’; this is the default state from the

factory. When one or more bits in the nVWLDR are set

to ‘1’, the BPNV bit will be ‘0’ from that point forward,

even after power-up.

4.6.3

WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that enables the WP# pin.

The Write-Protect (WP#) pin and the Write-Protect

Enable (WPEN) bit control the programmable

hardware write-protect feature. Setting the WP# pin to

low and the WPEN bit to ‘1’ enable hardware write

protection. To disable hardware write protection, set

either the WP# pin to high or the WPEN bit to ‘0’. There

is latency associated with writing to the WPEN bit. Poll

the BUSY bit in the STATUS register or wait TWPEN for

the completion of the internal, self-timed write

operation. When the chip is hardware write-protected,

only write operations to Block Protection and

Configuration registers are disabled. See

Section 4.2

“Hardware Write Protection” and Table 4-1 for more

information about the functionality of the WPEN bit.

WPEN

Write-Protection Pin (WP#) Enable

1 = WP# enabled

0 = WP# disabled

0(2)

R/W

TABLE 4-3:

CONFIGURATION REGISTER (CONTINUED)

Bit

Name

Function

Default at

Power-up

Read/Write (R/W)

Note 1: Default at Power-up is ‘0’.

2: Factory default setting. This is a nonvolatile bit; default at power-up will be the setting prior to power-down.

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