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MCP3460RT-E/2LX Datasheet(PDF) 52 Page - Microchip Technology

Part # MCP3460RT-E/2LX
Description  Two-Channel, 153.6 kSPS, Low-Noise, 16-Bit Delta-Sigma ADC with Internal Voltage Reference
PDF  103 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3460RT-E/2LX Datasheet(HTML) 52 Page - Microchip Technology

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MCP3460R
DS20006975A page 52
 2025 Microchip Technology Inc. and its subsidiaries
FIGURE 5-12:
ADC Output and IRQ Behavior with Digital Offset Calibration Enabled.
5.13.2
DIGITAL GAIN ERROR CALIBRATION
The Gain Error Calibration register (GAINCAL,
address: 0xA) is an unsigned 24-bit register that holds
the digital gain error calibration value, GAINCAL.
Equation 5-8 calculates the GAINCAL multiplier.
EQUATION 5-8:
GAINCAL CALIBRATION
VALUE (MULTIPLIER
VALUE)
For the MCP3460R device, the gain error calibration is
done by multiplying the GAINCAL value to the ADC out-
put code. The last byte of the GAINCAL register (GAIN-
CAL[7:0]) is ignored and internally reset to 0x00 during
the calibration; therefore, the multiplication just takes
into account the GAINCAL[23:8] bits.
The gain error calibration value range in equivalent
voltage is [0; 2-2-15], which can cancel any possible
gain error in the ADC and in the system. The gain
error calibration is made with a simple add-and-shift
circuit clocked on DMCLK and induces a pipeline
delay of TGCAL = 15 DMCLK periods. This pipeline
delay acts as a delay on the data ready interrupt
position that is shifted by TGCAL = 15 DMCLK periods.
During this delay, the converter can process the next
conversion, the delay does not shift the next conver-
sion and does not change the Conversion Time,
TCONV. Enabling the gain error calibration will affect
the next conversion result. The conversion result
already held in the ADCDATA register (0x0) is not
modified when the EN_GAINCAL is set to ‘1’, but the
next one will take the offset calibration into account.
Changing the GAINCAL register to a new value will
not affect the current ADCDATA value, but the next
one (after a data ready interrupt) will take the new
GAINCAL value into account. Figure 5-13 shows the
different cases and their associated effects on the
ADCDATA register and the IRQ output.
ADC DATA
REGISTER
VALUE
SPI
Wri te
EN _OFFC AL = 1
IRQ
ADC
STATUS
Data 2 Conversion
Data 1 Conversion
Data 3 Conversion
DATA1
DATA0
DATA2 + OFFSETCAL1
Wri te
OFFSE TCA L[23: ] = OFFSE TCA L1
Wri te
OFFSE TCA L[2 3 : ] = OFFSE TCA L2
Data 4 Conversion
DATA3 + OFFSETCAL2
GAINCAL (V/V) = (GAINCAL[23:8] unsigned decimal
code)/32768



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