MCP3460RT-ESLASH2LX datasheet(69/103 Pages) MICROCHIP

69 / 103 page

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DS20006975A page 69

MCP3460R

sequence. The CRC checksum on communications

can be enabled or disabled through the EN_CRCCOM

bit in the CONFIG3 register. The CRC message

ensures the integrity of the read sequence bits

transmitted on the SDO pin.

The CRC checksum in the MCP3460R device uses the

16-bit CRC-16 ANSI polynomial as defined in the IEEE

802.3 Standard: x16 +x15 +x2 +1.

This polynomial can also be noted as 0x8005. CRC-16

detects all single and double-bit errors, all errors with

an odd number of bits, all burst errors of 16 bits in

length or less and most errors for longer bursts. This

allows an excellent coverage of the SPI communication

errors that can occur in the system and heavily reduces

the risk of a miscommunication, even under noisy

environments.

When enabled, the CRC checksum (CRCCOM[15:0])

is propagated on SDO after each read communication

sequence.

In case of a Static Read command, the checksum is

propagated after each register read. In case of an

Incremental Read command, the checksum is

propagated after the last register read in the register

map (address: 0xF). Figure 6-11 and Figure 6-12 show

typical read communications in Static Read and

Incremental Read modes, respectively, when the

EN_CRCCOM bit is enabled. Since the STATUS byte

is propagated on SDO, it is part of the first message,

and therefore, it is included in the calculation of the first

checksum. For subsequent checksum calculations, the

message only contains the registers that are effectively

read in between two checksums.

The CRC-16 format displayed on the SDO pin depends

on the CRC_FORMAT bit in the CONFIG3 register (see

Figure 6-10). It can have a 16-bit or 32-bit format to be

compatible with both 16-bit and 32-bit MCUs. The

CRCCOM[15:0] bits calculated by the device do not

depend on the format (the device always calculates a

16-bit only CRC checksum).

FIGURE 6-10:

CRC Format Table for Read

Communications.

The CRC calculation computed by the device is fully

compatible with the CRC hardware contained in the

Direct Memory Access (DMA) of the PIC24 and PIC32

MCU product lines. The CRC message that should be

considered in the PIC® device DMA is the

concatenation of the read sequence and its associated

checksum. When the DMA CRC hardware computes

this extended message, the resulted checksum should

be 0x0000. Any other result indicates that a

miscommunication has occurred and that the current

communication sequence should be stopped and

restarted.

FIGURE 6-11:

SPI Static Read with Communication CRC Enabled.

CRCCOM[15:0]

0x0000

CRC_FORMAT = 0: 16-Bit

(Default)

CRC_FORMAT = 1: 32-Bit

CRC Checksum

ADDR

Roll-over

ADDRESS SET

Don’t Care

SCK

SDI

SDO

High-Z

ADDR

CMD[7:6] + ADDR + 01

Complete READ sequence including STATUS Byte

= First Message for CRC Calculation

...

Don’t Care

COMMAND

BYTE

CRC Checksum

ADDR

CRC Checksum

16x or 32x

Depending on

CRC format

16x or 32x

Depending on

CRC format

Depends on

ADDR

Depends on

ADDR

STATUS

BYTE

New message

New checksum

First checksum

MCP3460RT-E/2LX Datasheet(PDF) 69 Page - Microchip Technology

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