MCP3460RT-ESLASH2LX datasheet(71/103 Pages) MICROCHIP

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DS20006975A page 71

MCP3460R

When the part write access is unlocked, the interrupt on

the IRQ pin clears immediately and the two other inter-

rupt mechanisms are cleared when the interrupt is read

(read STATUS byte or read IRQ register). The CRC

interrupt can occur even if the IRQ pin is configured as

the MDAT modulator output. In this case, the interrupt

stays present and forces a logic low output on this pin

as long as the LOCK[7:0] register is locked (LOCK[7:0]

0xA5).

At power-up, the interrupt is not present and the

writing its configuration, the user needs to lock the

bits) to be able to use the interrupt flag and to calculate

the checksum of the register map.

6.8

Interrupts Description

The MCP3460R device incorporates multiple interrupt

mechanisms to be able to synchronize the device with

an MCU and to warn against external perturbations.

There are four events that can generate interrupt flags:

• Conversion Start

• Data Ready

•POR

• CRC Error on the Register Map Configuration

Additionally, there are three independent interrupt

mechanisms that allow the MCP3460R device to be

implemented in many different applications and config-

urations. A summary of the different mechanisms is

available in Table 6-3.

6.8.1

CONVERSION DATA READY

INTERRUPT

The data ready interrupt happens when a new

conversion is ready to be read on the ADCDATA register.

This event happens synchronously with DMCLK and at

each end of conversion. This interrupt is implemented

with three different and independent mechanisms:

STATUS byte on SDO, IRQ register Status bit and IRQ

pin state.

STATUS byte on SDO. When the interrupt

occurs on the next STATUS byte transmitted on

SDO, the DR_STATUS bit will be logic low. Once

the STATUS byte has been transmitted, the

DR_STATUS bit appears as ‘1’ until a new

interrupt is present. If the interrupt occurs

between two STATUS byte transmissions, the

DR_STATUS bit on SDO will appear as equal to

‘0’ on the second reading.

IRQ register Status bit. When the interrupt

occurs, the DR_STATUS bit in the IRQ register

is set to ‘0’. Once the IRQ register has been fully

read, this DR_STATUS bit is reset to ‘1’. If the

interrupt occurs between two readings of the

IRQ register, the IRQ register Status bit appears

as equal to ‘0’ on the second reading.

TABLE 6-3:

INTERRUPT DESCRIPTION SUMMARY TABLE

Interrupt Flag Type

Description

Clearing Procedure

STATUS Byte

Three Status bits (DR_STATUS,

CRCCFG_STATUS, POR_STATUS) are

latched together after device address

detection and clocked out during each

command on the SDO STATUS byte.

Cleared when STATUS byte clocking is finished

(on the last SCK falling edge).

IRQ Register Status

Bits

IRQ register Status bits can be read when

reading the address 0x5 (IRQ register).

The IRQ latching occurs at the beginning

of the IRQ register reading.

Cleared when the IRQ register reading is

finished (on the last SCK falling edge).

IRQ Pin State

• When IRQ_MODE[1] = 0, the IRQ pin

can be asserted to logic low by any of

the interrupts.

• When IRQ_MODE[1] = 1, only POR

and CRC interrupts can assert the

IRQ pin to logic low.

• Conversion start interrupt is automatically

cleared at the beginning of a new

conversion cycle after a TSTP timing.

• DR interrupt is cleared by the first SCK

falling edge of an ADC read, or

automatically 16 DMCLKs before a new

data ready in Continuous Conversion mode

or in Scan mode.

• POR interrupt is cleared on the first CS

falling edge when both AVDD and DVDD

monitoring circuits detect that their power

supply is over their respective thresholds.

• CRCCFG interrupt is cleared when the

device is unlocked (writing 0xA5 to LOCK

start/restart conversion is performed.

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