MCP3460RT-ESLASH2LX datasheet(70/103 Pages) MICROCHIP

70 / 103 page

MCP3460R

DS20006975A page 70

 2025 Microchip Technology Inc. and its subsidiaries

FIGURE 6-12:

SPI Incremental Read with Communication CRC Enabled.

6.6

Locking/Unlocking Register Map

Write Access

The MCP3460R digital interface includes an advanced

security feature that allows locking or unlocking the

miscommunication that can corrupt the desired config-

uration of the device, especially an SPI read becoming

an SPI write because of the noisy environment.

The last register address of the incremental write loop

(0xD: LOCK) contains the LOCK[7:0] bits. If these bits

are equal to the password value (0xA5), the register

map write access is not locked. Any write can take

place and the communications are not protected. The

MCP3460R device, by default after POR, is in an

unlocked state (LOCK[7:0] = 0xA5).

When the LOCK[7:0] bits are not equal to 0xA5, the

and therefore, the full device configuration is write-

protected. Any write to an address other than 0xD will

yield no result. All the register addresses, except the

address 0xD, become read-only. In this case, if the user

wants to change the configuration, the LOCK[7:0] bits

have to be reprogrammed back to 0xA5 before sending

the desired Write command.

The LOCK[7:0] bits are located in the last register of the

Incremental Write address loop, so the user can pro-

gram the entire register map, starting from 0x1 to 0xD,

within one continuous write sequence and then lock the

configuration at the end of the sequence by writing all

zeros (for example) in the 0xD address.

6.7

CRC-16 Checksum

To prevent internal corruption and to provide additional

security on the register map configuration, the

MCP3460R device includes an automatic and

continuous CRC checksum calculation on the full

the same as the communication CRC checksum

described

Section 6.5

“Securing

Read

Communications through CRC-16 Checksum”.

This calculation takes the contents of the register map,

from addresses 0x1 to 0xF, and produces a checksum

which is held in the CRCCFG[15:0] bits located in the

CRCCFG register (address: 0xF). The CRC checksum

for the register map uses the 16-bit CRC-16 ANSI poly-

nomial as defined in the IEEE 802.3 Standard:

x16 +x15 +x2 +1.

Since this feature is intended to protect the

configuration of the device, this calculation is run

continuously only when the register map is locked

(LOCK[7:0]), which is different than 0xA5 (see

Section 6.6 “Locking/Unlocking Register Map

Write Access”). If the register map is unlocked (for

example, after POR), the CRCCFG[15:0] bits are

cleared and no CRC is calculated.

The

DR_STATUS,

CRCCFG_STATUS

and

POR_STATUS bits are set to ‘1’ (default) and the

CRCCFG[15:0] bits are set to ‘0’ (default) for this calcu-

lation, as they could vary and lead to unwanted CRC

errors.

After the DR_STATUS, CRCCFG_STATUS and

POR_STATUS bits are cleared (with a read on the IRQ

be verified by reading all registers in an Incremental

Read sequence and by using the CRC communication.

At the second incremental read loop, the checksum

provided by the CRC communication must be equal to

all zeros if the checksum on the register map is correct.

The checksum will be calculated for the first time in

11 DMCLK periods. This first value will then be the

reference checksum value and will be latched internally

until an unlocking of the register map occurs. The

checksum will then be calculated continuously every

11 DMCLK periods and checked against the reference

checksum.

If the checksum is different than the reference, an

interrupt flag will be generated on the CRCCFG_STATUS

bit within the STATUS byte on SDO, on the

CRCCFG_STATUS bit in the IRQ register and on the

IRQ output pin. The interrupt flag is maintained on all

three mechanisms until the register map write access

is unlocked.

Don’t Care

SCK

SDI

SDO

Depends on

ADDR

...

ADDR = 0xF

CMD[7:6] + ADDR + 11

Complete READ sequence including STATUS Byte

= First Message for CRC Calculation

ADDR + 1

Depending on

ADDR+1

...

16x

Depends on

Data Format

ADDR = 0x0

...

New Message

ADDR = 0x1

...

24x

ADDR = 0xF

Don’t Care

COMMAND

BYTE

CRC Checksum

16x or 32x

Depending on

CRC format

16x or 32x

Depending on

CRC format

CRC Checksum

(not part of register map)

New Checksum

First Checksum

STATUS

BYTE

ADDR

...

0xF

Complete

READ

sequence

Roll-over

ADDRESS SET

0x0

...

High-Z

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