MCP3460RT-ESLASH2LX datasheet(57/103 Pages) MICROCHIP

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DS20006975A page 57

MCP3460R

The VCM reading is susceptible to the gain and offset

errors of the ADC, which should be calibrated to obtain

a precise internal Common-mode measurement.

5.15.4

DELAY BETWEEN CONVERSIONS

WITHIN A SCAN CYCLE (DLY[2:0])

While the ADC and multiplexer are optimized to switch

from one channel to another instantaneously, it may not

be the case of an application that requires additional

settling time to overcome the transition. The device can

insert an additional delay between each conversion of

the Scan cycle.

The delay value is controlled by the DLY[2:0] bits

located in the SCAN register (SCAN[23:20]). See

Table 5-15.

The delay is only added in between two conversions of

the same Scan cycle. There is no delay added at the

end or the beginning of each Scan cycle due to the

DLY[2:0] bits setting.

During this delay, the ADC is internally kept in Standby

mode (ADC_MODE[1:0] = 10 internally, but the

ADC_MODE[1:0] bits are always read as ‘11’ through

the SPI interface).

The analog multiplexer switches to the next selected

input at the end of each conversion (i.e., at the begin-

ning of the added delay, so that the application has

additional time to settle properly).

5.15.5

DELAY BETWEEN SCAN CYCLES

(TIMER[23:0])

During Continuous mode, Scan cycles are processed

continuously, one after another, separated by a time

delay (TTIMER_SCAN), which is defined by the TIMER

ADC is automatically placed into a power-saving mode

(Standby or ADC Shutdown). The TTIMER_SCAN delay

offers better power efficiency for applications which run

a Scan sequence periodically. Since the delay can be

very long, it allows synchronous applications with very

slow update rates without having to use an external

timer. The TIMER

defines

the

time,

TTIMER_SCAN, between cycles with a 24-bit unsigned

value going from 0 to 16777215 DMCLK periods.

Table 5-16 details the TIMER values with respect to the

TIMER[23:0] code.

The internal TIMER counter decrements from the

TTIMER_SCAN value to 0 and launches the new Scan

cycle.

If the TTIMER_SCAN value is greater than TADC_SETUP

(256 DMCLK periods), the MCP3460R will enter ADC

Shutdown mode (ADC_MODE is set to ‘00’ internally)

at each end of a Scan cycle. When the internal TIMER

counter reaches 256, the MCP3460R starts the ADC

during a TADC_SETUP time to be ready to convert when

the internal counter reaches 0.

If the TTIMER_SCAN value is less than TADC_SETUP, the

MCP3460R will be placed in Standby mode between

Scan cycles (ADC_MODE is set to ‘10’ internally).

ADC_MODE[1:0] bits in the CONFIG0 register can only

be read as ‘11’ by the SPI interface during the entire

Scan cycle and between Scan cycles.

5.16

A/D Conversion Automatic Reset

and Restart Feature

When the A/D conversions are running, the user can

change the device configuration through the SPI inter-

face by writing any register. Some register settings

directly impact the conversion results and lead to

invalid ADC data if they are changed within a

conversion.

The device incorporates an automatic reset and restart

feature for the A/D conversions to avoid these invalid

data. Some register writes with the SPI interface during

a conversion automatically reset and restart the A/D

conversion with the new settings.

The automatic reset and restart feature behavior

depends on the register bits that are written by the SPI

interface.

TABLE 5-15:

DELAY BETWEEN

CONVERSIONS WITHIN A

SCAN CYCLE

DLY[2:0]

Delay Value

(DMCLK Periods)

111

512

110

256

101

128

100

011

010

001

000

TABLE 5-16:

TIMER DELAY VALUE

BETWEEN SCAN CYCLES

TIMER[23:0]

TTIMER_SCAN Delay

Value

(DMCLK Periods)

111111111111111111111111

16777215

111111111111111111111110

16777214

100000000000000000000000

8388608

000000000000000000000001

000000000000000000000000

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