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MCP3460RT-E/2LX Datasheet(PDF) 79 Page - Microchip Technology |
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MCP3460RT-E/2LX Datasheet(HTML) 79 Page - Microchip Technology |
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79 / 103 page ![]() 2025 Microchip Technology Inc. and its subsidiaries DS20006975A page 79 MCP3460R 8.0 INTERNAL REGISTERS The MCP3460R device has a total of 16 internal registers composed of volatile memory. These registers are sequentially accessible and are included in Table 8-1. TABLE 8-1: INTERNAL REGISTERS SUMMARY Address Register Name Numbe r of Bits R/W Description 0x0 ADCDATA 4/16/32 R Latest Analog-to-Digital (A/D) conversion data output value (16 or 32 bits depending on DATA_FORMAT[1:0]) or modulator output stream (4-bit wide) when in MDAT Output mode. 0x1 CONFIG0 8 R/W Voltage Reference mode, ADC Operating mode, Main Clock mode. 0x2 CONFIG1 8 R/W Prescale and OSR settings 0x3 CONFIG2 8 R/W ADC boost and gain settings, auto-zeroing settings for analog multiplexer, voltage reference and ADC. 0x4 CONFIG3 8 R/W Conversion mode, data and CRC format settings. Enable for cyclic redundancy check (CRC) on communications. Enable for digital offset and gain error calibrations. 0x5 IRQ 8 R/W Interrupt request (IRQ) status bits and IRQ mode settings. Enable for Fast commands and for conversion start pulse. 0x6 MUX 8 R/W Analog multiplexer input selection (MUX mode only) 0x7 SCAN 24 R/W Scan mode settings 0x8 TIMER 24 R/W Delay value for TIMER between scan cycles 0x9 OFFSETCAL 24 R/W ADC digital offset calibration value 0xA GAINCAL 24 R/W ADC digital gain calibration value 0xB RESERVED 24 R/W Unimplemented 0xC RESERVED 8 R/W Unimplemented 0xD LOCK 8 R/W Password value for SPI Write mode locking 0xE RESERVED 16 R/W Unimplemented 0xF CRCCFG 16 R CRC checksum for device configuration |
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