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MCP3460RT-E/2LX Datasheet(PDF) 83 Page - Microchip Technology |
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MCP3460RT-E/2LX Datasheet(HTML) 83 Page - Microchip Technology |
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83 / 103 page  2025 Microchip Technology Inc. and its subsidiaries DS20006975A page 83 MCP3460R 8.4 CONFIG2 REGISTER Name Bits Address Cof CONFIG2 8 0x3 R/W REGISTER 8-4: CONFIG2: CONFIGURATION REGISTER 2 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 BOOST[1:0] GAIN[2:0] AZ_MUX AZ_REF RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 BOOST[1:0]: ADC Bias Current Selection 11 = ADC channel has current x 2 10 = ADC channel has current x 1 (default) 01 = ADC channel has current x 0.66 00 = ADC channel has current x 0.5 bit 5-3 GAIN[2:0]: ADC Gain Selection 111 = Gain is x64 (x16 analog, x4 digital) 110 = Gain is x32 (x16 analog, x2 digital) 101 = Gain is x16 100 = Gain is x8 011 = Gain is x4 010 = Gain is x2 001 = Gain is x1 (default) 000 = Gain is x1/3 bit 2 AZ_MUX: Auto-Zeroing MUX Setting 1 = ADC auto-zeroing algorithm is enabled. This setting multiplies the conversion time by 2 and does not allow Continuous Conversion mode operation, which is replaced by a series of consecutive One-Shot mode conversions. 0 = Analog input multiplexer auto-zeroing algorithm is disabled (default). bit 1 AZ_REF: Auto-Zeroing Reference Buffer Setting 1 = Internal voltage reference buffer chopping algorithm is enabled. This setting has no effect when external voltage reference is selected (VREF_SEL = 0 in CONFIG0 register) (default). 0 = Internal voltage reference buffer chopping auto-zeroing algorithm is disabled. bit 0 RESERVED: Reserved Bit Must remain set to ‘1’. |
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