M65KG256AB datasheet(12/51 Pages) STMICROELECTRONICS

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3 Commands

M65KG256AB

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Commands

The M65KG256AB recognizes a set of commands that are obtained by specific statuses of

Chip Enable, E, Column Address Strobe, CAS, Row Address Strobe, RAS, Write Enable, W,

and address inputs. Refer to Table 3: Commands, in conjunction with the text descriptions

below.

Figure 3: Simplified Command State Diagram shows the operations that are performed when

each command is issued at each state of the DDR LPSDRAM.

3.1

Mode Register Set command (MRS)

The Mode Register Set command is used to configure the Burst Length, Burst Type and CAS

Latency of the device by programming the Mode Register.

The command is issued with KE held High, with BA0, BA1 and A10 set to ‘0’, and E, RAS, CAS

and W driven Low, VIL. The value of address inputs A0 to A7 determines the Burst Length,

Burst Type and CAS Latency of the device (see Table 7: Mode Register Definition and

Figure 19: Mode Register/Extended Mode Register Set Commands AC Waveforms):

●

The Burst Length (2, 4, 8, 16 Words) is programmed using the address inputs A2-A0

●

The Burst Type (sequential or interleaved) is programmed using A3.

●

The CAS Latency (3 Clock cycles) is programmed using A6-A4.

It is required to execute a Mode Register Set command at the end of the Power-up sequence.

Once the command has been issued, it is necessary to wait for at least two clock cycles before

issuing another command.

3.2

Extended Mode Register Set command (EMRS)

The Extended Mode Register Set command is used to configure the low-power features of the

device by programming the Extended Mode Register.

The command is issued with KE held High, BA0 at ‘0’, BA1 at ‘1’, A10 at ‘0’, by driving E, RAS,

CAS and W, Low, VIL. The value of address inputs A0 to A9 determines the Driver Strength, the

part of the array that is refreshed during Self Refresh and the Automatic Temperature

Compensated Self Refresh feature (see Table 8: Extended Mode Register Definition and

Figure 19: Mode Register/Extended Mode Register Set Commands AC Waveforms):

●

The part of the array to be refreshed (all banks, Bank A and B, Bank A only) during Self

Refresh is set using A2-A0.

●

The Driver Strength (full, 1/2 strength, 1/4 strength, 1/8 strength) is set using bits A6-A5

●

The Automatic temperature Compensated Self Refresh feature is always enabled (A9 set

to ‘0’).

It is required to execute an Extended Mode Register Set command at the end of the Power-up

sequence. Once the command has been issued, it is necessary to wait for at least two clock

cycles before issuing another command.

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