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M65KG256AB Datasheet(PDF) 17 Page - STMicroelectronics |
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M65KG256AB Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 51 page ![]() M65KG256AB 3 Commands 17/51 Table 3. Commands Command(1) 1. X = Don’t Care (VIL or VIH); V = Valid Address Input. Symbol KEn-1 (2) 2. Clock Enable KE must be stable at least for one clock cycle. KEn (2) E RAS CAS W BA1 BA0 A0-A9, A11-A12 A10 Mode Register Set MRS VIH VIH VIL VIL VIL VIL VIL VIL MR/EMR Data(3) 3. MR and EMR data is the value to be written in the Mode Register and Extended Mode Register, respectively. VIL Extended Mode Register Set EMRS VIH MR/EMR Data(3) Bank (Row) Activate ACT VIH VIH VIL VIL VIH VIH V V Row Address Read READ VIH VIH VIL VIH VIL VIH VV Column Address VIL (4) 4. If A10 is Low, VIL, when issuing the command, the row remains active at the end of the operation. Read with Auto Precharge READA VIH (5) 5. If A10 is High, VIH, when issuing the command, an automatic precharge cycle is performed at the end of the operation and the row reverts to the Idle mode. Burst Read Terminate BST VIH VIH VIL VIH VIH VIL XX X Write WRIT VIH VIH VIL VIH VIL VIL VV Column Address VIL (4) Write with Auto Precharge WRITA VIH (5) Precharge Selected Bank PRE VIH VIH VIL VIL VIH VIL V(6) 6. If A10 is Low, VIL, when issuing the command, only the bank selected by BA0-BA1 is precharged (BA0-BA1 should be valid). V(6) X VIL (6) Precharge All Banks PALL X(7) 7. If A10 is High, VIH, when issuing the command, all the banks are precharged and BA0-BA1 are Don’t Care. X(7) X VIH (7) Self-Refresh Entry(8) 8. All the banks must be idle before executing this command. SELF VIH VIL VIL VIL VIL VIH XX X X Self Refresh Exit SELFX VIL VIH VIH XX X XX X VIL VIH VIH VIH Auto Refresh(8) REF VIH VIH VIL VIL VIL VIH XX X Power-Down Entry(8) PDEN VIH VIL VIH XX X XX X VIL VIH VIH VIH Power-Down Exit PDEX VIL VIH VIH XX X XX X VIL VIH VIH VIH Deep Power-down Entry(8) DPDEN VIH VIL VIL VIH VIH VIL XX X Deep Power-down Exit DPDEX VIL VIH XX X X X X X |
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